Voltage mode Gray code A/D converters, such as that of FIG. 1A, are based on a series connection of analog operators, one for each bit, each of which is designed to process the following algorithm:Vout=abs[2(Vin−Vref)]
where                Vref=0.5 Vin full scale        
Prior to taking the absolute value, the sign of (Vin−Vref) is observed and determines the logic state, one or zero, of each respective bit. For the MSB (most significant bit) a positive polarity remainder equals a logic one, a negative remainder equals a logic zero. The converse is true for all successive lower order bits, positive remainder equals logic zero, and negative remainder equals one. Utilizing this rule, the output of the ADC is Gray code proportional to the analog input Vin. FIG. 2 shows a comparison of straight binary code vs. Gray code.
The remainder is multiplied by 2 before the absolute value is taken and passed on to the next succeeding stage. This allows normalization of Vref to a constant single value for each stage and reduces the accuracy requirement of each succeeding stage by a factor of 2.
Unlike other types of A/D converters, the Gray code converter requires no clocking of each bit. Ideally, the input voltage propagates through the circuit and produces valid code after a delay time equal to the summation of delay times associated with each analog operator.
The Gray code is an un-weighted binary code that changes by only one bit for each incremental increase or decrease in LSB value. This characteristic contrasts sharply with straight binary where all bits may be changing for a one bit incremental change in value. For example, the code change for the half-full-scale major carry of an 8 bit code is 01111111 to 10000000. As a result, an ADC with intrinsic Gray code output is well suited to asynchronous strobing of the data output without being susceptible to large scale errors.
Most existing implementations of the aforementioned Gray code algorithm take on the form, in one way or another, of the block diagram in FIG. 1B. Note that this architecture places a comparator, C1 in the signal path. A valid signal cannot move forward to the next stage until C1 has resolved the polarity of the difference between Vin and Vref and closed the appropriate switch, S1 or S2, to generate the absolute value output. Switch closure, be it voltage mode or current mode, introduces discontinuities in the signal path. All of the above significantly increases the propagation delay through each stage.
One self-steering architecture, as proposed by F. D. Waldauer (U.S. Pat. No. 3,187,325), presents an ideal case for voltage steering but is not implementable in a practical sense due to a lack of isolation between stages and the resultant instabilities created by parasitic positive feedback loops.
The Waldauer architecture is based on a balanced differential, voltage routing topology. This disclosure describes a balanced differential current routing topology.
The Waldauer architecture has fundamental issues with operational amplifier stability in its implementation due to poor analog operator input-output isolation.